the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3

Packet : 81404611pcm.rar filelist
hw4
hw4\0.mgf
hw4\1.mgf
hw4\3.mgf
hw4\bde.set
hw4\compile
hw4\compile\contents.lib~
hw4\compile\hw4.epr
hw4\compile\hw4.erf
hw4\compile\sources.sth
hw4\compile.cfg
hw4\elaboration.log
hw4\hw4.adf
hw4\hw4.LIB
hw4\hw4.wsp
hw4\log
hw4\log\console.log
hw4\projlib.cfg
hw4\src
hw4\src\pcm.awf
hw4\src\pcm.vhd
hw4\src\test_pcm.vhd

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