introduced several cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture ie, the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the microcontroller has 8xC251SA/SB/SP/SQ 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to efficiently execute C code. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data

Packet : 82597embedded system paper1.zip filelist
cast_c8051.pdf
MCU 架构介绍.doc
Multitasking operations require more hardware based RTOSes.doc
Programmers ramp for Internet enabled control for embedded devices.doc
可重构性设计技术的发展.doc
四倍带宽存储器技术.doc
基于RISC结构的多功能嵌入式处理器结构设计.doc
嵌入式存储器的设计方法和策略.doc
嵌入式系统设计中查找内存丢失的策略.doc
嵌入式系统设计中的存储碎片收集策略.doc
用低成本FPGA替代ASIC实现大批量生产.doc
解决优先级倒置问题的RTOS优先级调度策略.doc

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