into first place with the addition of VHDL code more complicated, just for reference.

Packet : 7544813489_full_adder.rar filelist
89_full_adder\89_Full_adder.flow.rpt
89_full_adder\89_Full_adder.map.rpt
89_full_adder\89_Full_adder.map.summary
89_full_adder\89_Full_adder.qpf
89_full_adder\89_Full_adder.qsf
89_full_adder\89_Full_adder.qws
89_full_adder\89_Full_adder.vhd
89_full_adder\89_full_adder_stim.vhd
89_full_adder\89_pack_2_0.vhd
89_full_adder\cmp_state.ini
89_full_adder\db\89_Full_adder.cbx.xml
89_full_adder\db\89_Full_adder.cmp.rdb
89_full_adder\db\89_Full_adder.db_info
89_full_adder\db\89_Full_adder.eco.cdb
89_full_adder\db\89_Full_adder.map.hdb
89_full_adder\db\89_Full_adder.map.qmsg
89_full_adder\db\89_Full_adder.sld_design_entry.sci
89_full_adder\db\89_Full_adder_cmp.qrpt
89_full_adder\db
89_full_adder\README.TXT
89_full_adder\talkback\89_Full_adder.map.talkback.xml
89_full_adder\talkback
89_full_adder

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