Fuzhou University EDA optional courses in all experimental code. VHDL description (vhd), and circuit (GdF)

Packet : 19854821[eda]vhdl.rar filelist
1002016p_Sa_2\Light_6.vhd
1002016p_Sa_2\light.vhd
1002016p_Sa_2\000.The Electronic Design Automation (EDA)
1002016p_Sa_2\1002016_EDA实验报告二.doc
1002016p_Sa_2
1002016p_Sa_3\tosin.vhd
1002016p_Sa_3\1002016_EDA实验报告三.doc
1002016p_Sa_3
1002016p_Sa_4\CNT8.VHD
1002016p_Sa_4\DISPLAY.GDF
1002016p_Sa_4\LED.VHD
1002016p_Sa_4\MUX8.VHD
1002016p_Sa_4\1002016_EDA实验报告四.doc
1002016p_Sa_4
1002016p_Sa_5\cnt10.vhd
1002016p_Sa_5
1002016p_Sa\1002016_EDA实验报告一.doc
1002016p_Sa\2endaddr.gdf
1002016p_Sa\2endaddr.jpg
1002016p_Sa\addr.vhd
1002016p_Sa\endaddr.gdf
1002016p_Sa\halfaddr.vhd
1002016p_Sa
1002016p_Sa_5\CNT8.VHD
1002016p_Sa_5\king8.gdf
1002016p_Sa_5\LED.VHD
1002016p_Sa_5\MUX8.VHD
1002016p_Sa_5\1002016_EDA实验报告五.doc
1002016p_Sa_clockHMS\cnt24.vhd
1002016p_Sa_clockHMS\cnt10.vhd
1002016p_Sa_clockHMS\cnt6.vhd
1002016p_Sa_clockHMS\CNT8.VHD
1002016p_Sa_clockHMS\king8.gdf
1002016p_Sa_clockHMS\LED.VHD
1002016p_Sa_clockHMS\MUX8.VHD
1002016p_Sa_clockHMS\this clock_18hH.60M.60S
1002016p_Sa_clockHMS\1002016_EDA实验报告七_CLOCK.doc
1002016p_Sa_clockHMS
1002016p_Sa_2\light_6.acf
1002016p_Sa_2\light_6.hif
1002016p_Sa_6\CNT8.VHD
1002016p_Sa_6\CONTROL.VHD
1002016p_Sa_6\LED.VHD
1002016p_Sa_6\MUX8.VHD
1002016p_Sa_6\MYREG.VHD
1002016p_Sa_6\cnt10.vhd
1002016p_Sa_6\king8.gdf
1002016p_Sa_6\1002016_EDA实验报告六.doc
1002016p_Sa_6
1002016p_Sa_6\CONTROL.VHD  MYREG.VHD  参考1002025

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