a complete MIPS CPU, innovative design, a student of Zhejiang University works with complete documentation, simulation and test documents, and can be directly integrated simulation.

Packet : 53607886mips_creative.rar filelist
MIPS
MIPS\说明.doc
MIPS\mips.doc
MIPS\ISE
MIPS\ISE\ISE.npl
MIPS\ISE\__projnav.log
MIPS\ISE\automake.log
MIPS\ISE\global_vhdl.prj
MIPS\ISE\.untf
MIPS\ISE\global_map.ngm
MIPS\ISE\global_map.ncd
MIPS\ISE\global_pad.csv
MIPS\ISE\global_pad.txt
MIPS\ISE\global.xpi
MIPS\ISE\main.prj
MIPS\ISE\main.cmd_log
MIPS\ISE\main.syr
MIPS\ISE\main_vhdl.prj
MIPS\ISE\main.lso
MIPS\ISE\main.ngr
MIPS\ISE\main.ngc
MIPS\ISE\main.stx
MIPS\ISE\main.bld
MIPS\ISE\main.ngd
MIPS\ISE\main.mrp
MIPS\ISE\main_map.ngm
MIPS\ISE\main_map.ncd
MIPS\ISE\main.pcf
MIPS\ISE\main.nc1
MIPS\ISE\main.ngm
MIPS\ISE\main.par
MIPS\ISE\main_pad.csv
MIPS\ISE\main.pad
MIPS\ISE\main_pad.txt
MIPS\ISE\main.ncd
MIPS\ISE\main.xpi
MIPS\ISE\main.placed_ncd_tracker
MIPS\ISE\main.routed_ncd_tracker
MIPS\ISE\main.pad_txt
MIPS\ISE\main.twx
MIPS\ISE\main.twr
MIPS\ISE\TEST.v
MIPS\ISE\main_timesim.nlf
MIPS\ISE\main_timesim.sdf
MIPS\ISE\main_timesim.v
MIPS\ISE\main.versim_par
MIPS\ISE\main.par_nlf
MIPS\ISE\main_TEST_v_tf.udo
MIPS\ISE\main_TEST_v_tf.tdo
MIPS\ISE\transcript
MIPS\ISE\vsim.wlf
MIPS\ISE\ISE.dhp
MIPS\ISE\work
MIPS\ISE\work\_info
MIPS\ISE\_ngo
MIPS\ISE\_ngo\netlist.lst
MIPS\ISE\xst
MIPS\ISE\xst\work
MIPS\ISE\xst\work\hdllib.ref
MIPS\ISE\xst\work\vlg2D
MIPS\ISE\xst\work\vlg2D\main.bin
MIPS\ISE\xst\work\vlg20
MIPS\ISE\xst\work\vlg20\Registers.bin
MIPS\ISE\xst\work\vlg47
MIPS\ISE\xst\work\vlg47\Execute.bin
MIPS\ISE\xst\work\vlg0A
MIPS\ISE\xst\work\vlg0A\Data_Memory.bin
MIPS\ISE\xst\work\vlg41
MIPS\ISE\xst\work\vlg41\Control.bin
MIPS\ISE\xst\work\vlg30
MIPS\ISE\xst\work\vlg30\Decode.bin
MIPS\ISE\xst\work\vlg62
MIPS\ISE\xst\work\vlg62\Fetch.bin
MIPS\ISE\xst\work\vlg3B
MIPS\ISE\xst\work\vlg3B\Code_Memory.bin
MIPS\ISE\xst\work\vlg15
MIPS\ISE\xst\work\vlg15\global.bin
MIPS\ISE\__projnav
MIPS\ISE\__projnav\coregen.rsp
MIPS\ISE\__projnav\runXst_tcl.rsp
MIPS\ISE\__projnav\ednTOngd_tcl.rsp
MIPS\ISE\__projnav\nc1TOncd_tcl.rsp
MIPS\ISE\__projnav\ISE_flowplus.gfl
MIPS\ISE\__projnav\ISE.gfl
MIPS\ISE\__projnav\global.xst
MIPS\ISE\__projnav\posttrc.log
MIPS\ISE\__projnav\main.xst
MIPS\ISE\__projnav\map.log
MIPS\ISE\__projnav\par.log
MIPS\ISE\__projnav\createTF.err
MIPS\ISE\__projnav\netgen_par_tcl.rsp
MIPS\ModelSim
MIPS\ModelSim\MIPS.mpf
MIPS\ModelSim\MIPS.cr.mti
MIPS\ModelSim\work
MIPS\ModelSim\work\_info
MIPS\ModelSim\work\main_test
MIPS\ModelSim\work\main_test\_primary.vhd
MIPS\ModelSim\work\main_test\verilog.asm
MIPS\ModelSim\work\main_test\_primary.dat
MIPS\ModelSim\work\main
MIPS\ModelSim\work\main\_primary.vhd
MIPS\ModelSim\work\main\verilog.asm
MIPS\ModelSim\work\main\_primary.dat
MIPS\ModelSim\work\@registers
MIPS\ModelSim\work\@registers\_primary.vhd
MIPS\ModelSim\work\@registers\verilog.asm
MIPS\ModelSim\work\@registers\_primary.dat
MIPS\ModelSim\work\@execute
MIPS\ModelSim\work\@execute\_primary.vhd
MIPS\ModelSim\work\@execute\verilog.asm
MIPS\ModelSim\work\@execute\_primary.dat
MIPS\ModelSim\work\@data_@memory
MIPS\ModelSim\work\@data_@memory\_primary.vhd
MIPS\ModelSim\work\@data_@memory\verilog.asm
MIPS\ModelSim\work\@data_@memory\_primary.dat
MIPS\ModelSim\work\@control
MIPS\ModelSim\work\@control\_primary.vhd
MIPS\ModelSim\work\@control\verilog.asm
MIPS\ModelSim\work\@control\_primary.dat
MIPS\ModelSim\work\@decode
MIPS\ModelSim\work\@decode\_primary.vhd
MIPS\ModelSim\work\@decode\verilog.asm
MIPS\ModelSim\work\@decode\_primary.dat
MIPS\ModelSim\work\@fetch
MIPS\ModelSim\work\@fetch\_primary.vhd
MIPS\ModelSim\work\@fetch\verilog.asm
MIPS\ModelSim\work\@fetch\_primary.dat
MIPS\ModelSim\work\@code_@memory
MIPS\ModelSim\work\@code_@memory\_primary.vhd
MIPS\ModelSim\work\@code_@memory\verilog.asm
MIPS\ModelSim\work\@code_@memory\_primary.dat
MIPS\ModelSim\work\global
MIPS\ModelSim\work\global\_primary.vhd
MIPS\ModelSim\work\global\verilog.asm
MIPS\ModelSim\work\global\_primary.dat
MIPS\Source
MIPS\Source\data_memory.v
MIPS\Source\registers.v
MIPS\Source\fetch.v
MIPS\Source\decode.v
MIPS\Source\control.v
MIPS\Source\execute.v
MIPS\Source\main.v
MIPS\Source\main_test.v
MIPS\Source\global.v
MIPS\Source\global.h.bak
MIPS\Source\code_memory.v.bak
MIPS\Source\code_memory.v

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