This is an ultrasonic launch control circuit design, a continuous single-carrier pulse.

9-12
....\db
....\..\emit.asm.qmsg
....\..\emit.cbx.xml
....\..\emit.cmp.cdb
....\..\emit.cmp.hdb
....\..\emit.cmp.kpt
....\..\emit.cmp.logdb
....\..\emit.cmp.rdb
....\..\emit.cmp.tdb
....\..\emit.cmp0.ddb
....\..\emit.dbp
....\..\emit.db_info
....\..\emit.eco.cdb
....\..\emit.eds_overflow
....\..\emit.fit.qmsg
....\..\emit.hier_info
....\..\emit.hif
....\..\emit.map.cdb
....\..\emit.map.hdb
....\..\emit.map.logdb
....\..\emit.map.qmsg
....\..\emit.pre_map.cdb
....\..\emit.pre_map.hdb
....\..\emit.psp
....\..\emit.rtlv.hdb
....\..\emit.rtlv_sg.cdb
....\..\emit.rtlv_sg_swap.cdb
....\..\emit.sgdiff.cdb
....\..\emit.sgdiff.hdb
....\..\emit.signalprobe.cdb
....\..\emit.sim.hdb
....\..\emit.sim.qmsg
....\..\emit.sim.rdb
....\..\emit.sim.vwf
....\..\emit.sld_design_entry.sci
....\..\emit.sld_design_entry_dsc.sci
....\..\emit.syn_hier_info
....\..\emit.tan.qmsg
....\..\wed.zsf
....\emit.asm.rpt
....\emit.done
....\emit.fit.rpt
....\emit.fit.smsg
....\emit.fit.summary
....\emit.flow.rpt
....\emit.map.rpt
....\emit.map.summary
....\emit.pin
....\emit.qpf
....\emit.qsf
....\emit.qws
....\emit.sim.rpt
....\emit.tan.rpt
....\emit.tan.summary
....\emit.vhd
....\emit.vwf

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