Verilog achieve optimization of 16 compared with the output can be greater than, less than, equal to. Modular design, which can be expanded to 32

Packet : 75448184comparators_16b.rar filelist
Comparators_16B
Comparators_16B\com.v
Comparators_16B\comparators.cr.mti
Comparators_16B\comparators.mpf
Comparators_16B\testbanche.v
Comparators_16B\transcript
Comparators_16B\vsim.wlf
Comparators_16B\work
Comparators_16B\work\@c@o@m@p1
Comparators_16B\work\@c@o@m@p1\verilog.asm
Comparators_16B\work\@c@o@m@p1\_primary.dat
Comparators_16B\work\@c@o@m@p1\_primary.vhd
Comparators_16B\work\@c@o@m@p16
Comparators_16B\work\@c@o@m@p16\verilog.asm
Comparators_16B\work\@c@o@m@p16\_primary.dat
Comparators_16B\work\@c@o@m@p16\_primary.vhd
Comparators_16B\work\@c@o@m@p2
Comparators_16B\work\@c@o@m@p2\verilog.asm
Comparators_16B\work\@c@o@m@p2\_primary.dat
Comparators_16B\work\@c@o@m@p2\_primary.vhd
Comparators_16B\work\@c@o@m@p4
Comparators_16B\work\@c@o@m@p4\verilog.asm
Comparators_16B\work\@c@o@m@p4\_primary.dat
Comparators_16B\work\@c@o@m@p4\_primary.vhd
Comparators_16B\work\@c@o@m@p8
Comparators_16B\work\@c@o@m@p8\verilog.asm
Comparators_16B\work\@c@o@m@p8\_primary.dat
Comparators_16B\work\@c@o@m@p8\_primary.vhd
Comparators_16B\work\@c@t@r@l
Comparators_16B\work\@c@t@r@l\verilog.asm
Comparators_16B\work\@c@t@r@l\_primary.dat
Comparators_16B\work\@c@t@r@l\_primary.vhd
Comparators_16B\work\@l@e@v@e@l
Comparators_16B\work\@l@e@v@e@l\verilog.asm
Comparators_16B\work\@l@e@v@e@l\_primary.dat
Comparators_16B\work\@l@e@v@e@l\_primary.vhd
Comparators_16B\work\com
Comparators_16B\work\com\verilog.asm
Comparators_16B\work\com\_primary.dat
Comparators_16B\work\com\_primary.vhd
Comparators_16B\work\testbanch
Comparators_16B\work\testbanch\verilog.asm
Comparators_16B\work\testbanch\_primary.dat
Comparators_16B\work\testbanch\_primary.vhd
Comparators_16B\work\_info

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