A 4* 4 matrix keyboard interface program Verilog Design (FPGA)

矩阵键盘
........\key1
........\....\.xhdl3.xref
........\....\cmp_state.ini
........\....\db
........\....\..\key1.asm.qmsg
........\....\..\key1.cbx.xml
........\....\..\key1.cmp.cdb
........\....\..\key1.cmp.hdb
........\....\..\key1.cmp.rdb
........\....\..\key1.cmp.tdb
........\....\..\key1.cmp0.ddb
........\....\..\key1.db_info
........\....\..\key1.eco.cdb
........\....\..\key1.fit.qmsg
........\....\..\key1.hier_info
........\....\..\key1.hif
........\....\..\key1.map.cdb
........\....\..\key1.map.hdb
........\....\..\key1.map.qmsg
........\....\..\key1.pre_map.cdb
........\....\..\key1.pre_map.hdb
........\....\..\key1.psp
........\....\..\key1.rtlv.hdb
........\....\..\key1.rtlv_sg.cdb
........\....\..\key1.rtlv_sg_swap.cdb
........\....\..\key1.sgdiff.cdb
........\....\..\key1.sgdiff.hdb
........\....\..\key1.signalprobe.cdb
........\....\..\key1.sld_design_entry.sci
........\....\..\key1.sld_design_entry_dsc.sci
........\....\..\key1.smp_dump.txt
........\....\..\key1.syn_hier_info
........\....\..\key1.tan.qmsg
........\....\..\key1_cmp.qrpt
........\....\key1.asm.rpt
........\....\key1.cdf
........\....\key1.done
........\....\key1.fit.eqn
........\....\key1.fit.rpt
........\....\key1.fit.summary
........\....\key1.flow.rpt
........\....\key1.map.eqn
........\....\key1.map.rpt
........\....\key1.map.summary
........\....\key1.pin
........\....\key1.pof
........\....\key1.qpf
........\....\key1.qsf
........\....\key1.qws
........\....\key1.tan.rpt
........\....\key1.tan.summary
........\....\key1.v
........\....\key1.v.bak

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