ASIC design of storage functionality, packet fifo, TCP/IP, Ethernet 2 Application

fifo write
..........\bench.v
..........\bench.v.bak
..........\data.txt
..........\data1.txt
..........\data1.txt.bak
..........\data2.txt
..........\fifo.v
..........\signal.xls
..........\st.v
..........\st.v.bak
..........\transcript
..........\vsim.wlf

..........\wave.do
..........\work
..........\....\bench
..........\....\.....\verilog.asm
..........\....\.....\_primary.dat
..........\....\.....\_primary.vhd
..........\....\write
..........\....\.....\verilog.asm
..........\....\.....\_primary.dat
..........\....\.....\_primary.vhd
..........\....\_info
..........\write.cr.mti
..........\write.mpf
..........\write.v
..........\write.v.bak

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