a directive to support the streamlining of the 16 RISC CPU can be integrated

Packet : 7346270016_risc_cpu.rar filelist
alu.v
cds.lib
clk1.v
counter.v
cpu.v
cpu_test.v
Fibonacci.txt
group_reg.v
hdl.var
machine.v
mux_a.v
mux_r.v
ncelab.log
nclaunch.key
nclaunch.dd
nclaunch.dd.bak
ncsim.key
ncsim.log
ncvlog.log
ram.v
register.v
risc_cpu.v
sum.txt
INCA_libs
INCA_libs\worklib
INCA_libs\worklib\.cdsvmod
INCA_libs\worklib\.inca.db.148.win32
INCA_libs\worklib\inca.win32.148.pak
waves.shm
waves.shm\waves.dsn
waves.shm\waves.trn
addreg.v

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