Introduction若若not Renyuan mpeg2 decode

lab4
....\cmp_state.ini
....\cpu.v
....\db
....\..\add_sub_c0h.tdf
....\..\add_sub_d0h.tdf
....\..\lab5.asm.qmsg
....\..\lab5.cbx.xml
....\..\lab5.cmp.cdb
....\..\lab5.cmp.hdb
....\..\lab5.cmp.logdb
....\..\lab5.cmp.rdb
....\..\lab5.cmp.tdb
....\..\lab5.cmp0.ddb
....\..\lab5.db_info
....\..\lab5.eco.cdb
....\..\lab5.eds_overflow
....\..\lab5.fit.qmsg
....\..\lab5.hier_info
....\..\lab5.hif
....\..\lab5.map.cdb
....\..\lab5.map.hdb
....\..\lab5.map.logdb
....\..\lab5.map.qmsg
....\..\lab5.pre_map.cdb
....\..\lab5.pre_map.hdb
....\..\lab5.psp
....\..\lab5.rtlv.hdb
....\..\lab5.rtlv_sg.cdb
....\..\lab5.rtlv_sg_swap.cdb
....\..\lab5.sgdiff.cdb
....\..\lab5.sgdiff.hdb
....\..\lab5.signalprobe.cdb
....\..\lab5.sim.hdb
....\..\lab5.sim.qmsg
....\..\lab5.sim.rdb
....\..\lab5.sim.vwf
....\..\lab5.sld_design_entry.sci
....\..\lab5.sld_design_entry_dsc.sci
....\..\lab5.smp_dump.txt
....\..\lab5.syn_hier_info
....\..\lab5.tan.qmsg
....\..\lab5_cmp.qrpt
....\..\lab5_sim.qrpt
....\lab2_sim.v
....\lab5.asm.rpt
....\lab5.done
....\lab5.fit.eqn
....\lab5.fit.rpt
....\lab5.fit.summary
....\lab5.flow.rpt
....\lab5.map.eqn
....\lab5.map.rpt
....\lab5.map.summary
....\lab5.pin
....\lab5.pof
....\lab5.qpf
....\lab5.qsf
....\lab5.qws
....\lab5.sim.rpt
....\lab5.sof
....\lab5.tan.rpt
....\lab5.tan.summary
....\lab5.vwf
....\memory.v
....\prog_ram.v

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