prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.

Packet : 59564338pci_target.zip filelist
CFG_DECODE.vhd
CFG_FSM.vhd
cfg_regs.vhd
CFG_ROM.vhd
CFG_SPACE.vhd
core_set.vhd
EROM_IF.vhd
G_PARITY.vhd
PCIT_CORE.vhd
PCIT_DB.pdf
pci_app.vhd
PCI_CMDADR.vhd
PCI_IO_VIRTEX.vhd
TARGET_FSM.vhd
USER_ALU.vhd
USER_APP.vhd

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