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UART_send
Downloaded:0
Verilog HDL send serial procedures, ACTEL Fusion FPGA in the success of the experiment, and share with everyone! ^ _ ^
Update
: 2008-10-13
Size
: 1.56kb
Publisher
:
whq
UART_rec
Downloaded:0
Verilog serial receive process, ACTEL Fusion FPGA in the experimental success and share with everyone! ^ _ ^
Update
: 2008-10-13
Size
: 1.54kb
Publisher
:
whq
scorce
Downloaded:0
FPGA-driven 1602LCD procedures, the success of the experiment on-board experiments, and the U.S. to share! ^ _ ^
Update
: 2008-10-13
Size
: 2.52kb
Publisher
:
whq
UART_LCD
Downloaded:0
Display module, using 51 single-chip UART port communications, has C language program, protel99se schematics, PCB design needs
Update
: 2008-10-13
Size
: 15.89kb
Publisher
:
唐润平
pca
Downloaded:0
pca matlab pca matlab
Update
: 2008-10-13
Size
: 1.67kb
Publisher
:
zzx
seethefunctiondescribe
Downloaded:0
FPGA in the study of bi-directional IO port. Pdf. And everyone to share! ^ _ ^
Update
: 2008-10-13
Size
: 113.7kb
Publisher
:
whq
chengxu
Downloaded:0
Signal measurement in real-time display the keyboard scanning delay 2 seconds
Update
: 2008-10-13
Size
: 25.22kb
Publisher
:
丁涛
ftps
Downloaded:0
CSR Bluetooth chip procedures ftp client server-side code has already been uploaded
Update
: 2008-10-13
Size
: 49.5kb
Publisher
:
lmc
ch2_2
Downloaded:0
VC++ 6.0 procedures for small game, in the hope that the comrades wanted to learn the game has to help.
Update
: 2008-10-13
Size
: 18.21kb
Publisher
:
shenshen
ch2_3
Downloaded:0
VC++ 6.0 procedures for small game, in the hope that the comrades wanted to learn the game has to help.
Update
: 2008-10-13
Size
: 18.15kb
Publisher
:
shenshen
ch2_4
Downloaded:0
VC++ 6.0 procedures for small game, in the hope that the comrades wanted to learn the game has to help.
Update
: 2008-10-13
Size
: 17.71kb
Publisher
:
shenshen
ch7_1
Downloaded:0
In VC++ 6.0 environment D3D configuration process, I hope this has interested friends have to help.
Update
: 2008-10-13
Size
: 49.25kb
Publisher
:
shenshen
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