VHDL-FPGA-Verilog List Page 16

VHDL-FPGA-Verilog list

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S03_基于ZYNQ的DMA与VDMA的应用开发 Downloaded：0: vivado DMA&VDMA example text of zynq
Update : 2024-06-12 Size : 9.24mb Publisher : kernelstory
S04_基于ZYNQ的HLS 图像算法设计基础 Downloaded：0: vivado image processing example text of zynq
Update : 2024-06-12 Size : 7.63mb Publisher : kernelstory
S05_example_Network Downloaded：1: vivado lwip example text of zynq
Update : 2024-06-12 Size : 3.24mb Publisher : kernelstory
sram Downloaded：0: Read and write SRAM memory block and Verilog code in FPGA
Update : 2024-06-12 Size : 1.32mb Publisher : bin_mm3
verilog实现dds Downloaded：1: The function of signal generator is realized based on FPGA, which is a good reference.
Update : 2024-06-12 Size : 2.47mb Publisher : sudochang
Rs通用编码 Downloaded：0: 适用各种体制的RS编码，Verilog实现，配置本原多项式参数即可
Update : 2019-08-29 Size : 1.71kb Publisher : 1314@someone
nexys3--ucf Downloaded：0: nexys3--ucf is the ucf file for nexys3 board
Update : 2019-09-06 Size : 4.08kb Publisher : jcljob
运动目标检测 Downloaded：1: shi xian yun dong jian ce .
Update : 2024-06-12 Size : 13kb Publisher : zero_lz
AHB-task-slave-master Downloaded：0: AHB master behavior level model, AHB slave model
Update : 2024-06-12 Size : 2kb Publisher : 鱼在在藻
Weighted-Round-Robin-Arbiter-master Downloaded：0: Verilog implementation of priority rotation algorithm with weight
Update : 2024-06-12 Size : 427kb Publisher : 鱼在在藻
module_average_filter Downloaded：0: Verilog implementation of a median filtering algorithm
Update : 2024-06-12 Size : 4kb Publisher : 兴鹏
camera_ov7725_sample Downloaded：2: Realize the camera ov7725 acquisition of video, output through VGA port. Fpga model EGO1, you can modify the XDC file.
Update : 2024-06-12 Size : 14.39mb Publisher : beTTer_every

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