Other resource List Page 11047

Other resource list

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yiraomis Downloaded：0: a complete medical-management system. Do not for commercial use!
Update : 2008-10-13 Size : 5mb Publisher : 戴利坚
enhancement Downloaded：0: the image processing of Matlab source, including contrast enhancement, histogram homogenization, and filtering. If interested welcome to download.
Update : 2008-10-13 Size : 32.3kb Publisher : 李连春
rtcticket实验（实时时钟） Downloaded：0: ARM7 rtcticket Experiment (real-time clock), the clock may help learning
Update : 2008-10-13 Size : 97.08kb Publisher : 百里情愁
地图图元修改工具 Downloaded：0: map plan amendments yuan batch tools can be selected to amend the map layer map yuan Style.
Update : 2008-10-13 Size : 16.09kb Publisher : 王静
8255按键练习 Downloaded：0: 8,255 inquiries through the keys, show different figures. K1 shows a, K2 showed 2, K1 and K2 showed three, and so forth. The most that can be shown 7.
Update : 2008-10-13 Size : 13.73kb Publisher : SKY
32位-33M 从模式(target)PCI接口参考设计_lattice Downloaded：0: 32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
Update : 2008-10-13 Size : 807.3kb Publisher : 陈旭
8051参考设计_Oregano System 提供_vhdl Downloaded：0: 8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
Update : 2008-10-13 Size : 648.99kb Publisher : 陈旭
CRC校验参考设计_xilinx_verilog Downloaded：0: IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
Update : 2008-10-13 Size : 87.82kb Publisher : 陈旭
CRC校验参考设计_xilinx_vhdl Downloaded：0: configurable CRC reference design for Xilinx VHDL
Update : 2008-10-13 Size : 48.71kb Publisher : 陈旭
DS12887时钟芯片编程 Downloaded：0: procedures for the use of function, to read clock chip seconds, hours, days, months, years, centuries, but also the date of its set-up time.
Update : 2008-10-13 Size : 18.34kb Publisher : SKY
红绿灯 Downloaded：0: simulated traffic lights and figures with the procedure. When all of the initial red, shows that the "hello" words. Then traffic lights to the "black, red and yellow, green, red, yellow red" state to do four cycle, but t
Update : 2008-10-13 Size : 25.24kb Publisher : SKY
ddr_verilog_xilinx Downloaded：1: DDR (double data rate) SDRAM controller reference design for Xilinx
Update : 2008-10-13 Size : 128.25kb Publisher : 陈旭

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