Other resource List Page 11050

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32位-33M 从模式(target)PCI接口参考设计_lattice Downloaded：0: 32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
Update : 2008-10-13 Size : 807.3kb Publisher : 陈旭
8051参考设计_Oregano System 提供_vhdl Downloaded：0: 8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
Update : 2008-10-13 Size : 648.99kb Publisher : 陈旭
CRC校验参考设计_xilinx_verilog Downloaded：0: IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
Update : 2008-10-13 Size : 87.82kb Publisher : 陈旭
CRC校验参考设计_xilinx_vhdl Downloaded：0: configurable CRC reference design for Xilinx VHDL
Update : 2008-10-13 Size : 48.71kb Publisher : 陈旭
DS12887时钟芯片编程 Downloaded：0: procedures for the use of function, to read clock chip seconds, hours, days, months, years, centuries, but also the date of its set-up time.
Update : 2008-10-13 Size : 18.34kb Publisher : SKY
红绿灯 Downloaded：0: simulated traffic lights and figures with the procedure. When all of the initial red, shows that the "hello" words. Then traffic lights to the "black, red and yellow, green, red, yellow red" state to do four cycle, but t
Update : 2008-10-13 Size : 25.24kb Publisher : SKY
ddr_verilog_xilinx Downloaded：1: DDR (double data rate) SDRAM controller reference design for Xilinx
Update : 2008-10-13 Size : 128.25kb Publisher : 陈旭
洗衣机 Downloaded：0: through different diode light, washing machines, said the different states. Who is changed, and turned around, washing, drying. Press P3_3, would cease.
Update : 2008-10-13 Size : 23.66kb Publisher : SKY
显示0到F Downloaded：0: drive using serial digital display shows each from 0 to F, to eliminate cycle, a request updated seconds.
Update : 2008-10-13 Size : 10.6kb Publisher : SKY
dds_quicklogic Downloaded：0: direct frequency synthesis, pioneered provide some source document is dedicated ESP
Update : 2008-10-13 Size : 66.85kb Publisher : 陈旭
I2C总线控制器 altera提供-VHDL Downloaded：0: I2C Bus Controller ALTERA the VHDL source code
Update : 2008-10-13 Size : 1.56mb Publisher : 陈旭
PCI总线仲裁参考设计，Quicklogic提供 Downloaded：0: PCI bus arbitration reference design, pioneered the Verilog code
Update : 2008-10-13 Size : 3.4kb Publisher : 陈旭

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